# Sr. ASIC Design Engineer

Hiring organization: [Ambarella](https://career.thegoodapps.co/organizations/ambarella)

Canonical page: https://career.thegoodapps.co/jobs/b954067b-628a-4382-9fc2-516fa9627de1

Listed on Ambarella's own careers site. Applications go to them directly.

- Seniority: Junior
- Location: US Headquarters
- Salary: 135000 – 170000 USD per year

## Summary

This role designs specialized processors for edge AI applications, focusing on video compression and image processing hardware using Verilog and SystemVerilog. It suits engineers with a computer engineering background who want to work on cutting-edge AI accelerators for robotics and embedded systems.

_Our summary, not Ambarella's wording._

## Skills named

Assembly Language, Perl, Python, SystemVerilog, Verilog

## Required

- Master's degree in Electrical, Electronics, or Computer Engineering
- 0-5 years of experience
- Understanding of computer architecture and logic design
- Knowledge of SystemVerilog and Verilog
- Knowledge of Python and Perl
- Knowledge of design verification and functional coverage
- Ability to write assembly language programs

## Nice to have

- Knowledge of logic synthesis and timing closure

Apply on Ambarella's site: https://ambarella.wd108.myworkdayjobs.com/en-US/Ambarella/job/US-Headquarters/Sr-ASIC-Design-Engineer_JR100082