# Physical Verification and EMIR Signoff Lead

Hiring organization: [Samsung Semiconductor](https://career.thegoodapps.co/organizations/samsung-semiconductor)

Canonical page: https://career.thegoodapps.co/jobs/b8d95cde-563f-4775-bd77-67841e891fe0

Listed on Samsung Semiconductor's own careers site. Applications go to them directly.

- Seniority: Senior

## Summary

This role leads physical verification and electrical analysis for advanced semiconductor chip designs at Samsung's major R&D center in India, overseeing signoff activities across multiple verification domains. It suits experienced chip designers who have worked on cutting-edge process nodes and can mentor junior engineers while driving process improvements.

_Our summary, not Samsung Semiconductor's wording._

## Skills named

Perl, Python, Tcl, Unix

## Required

- 11 to 18 years of experience in semiconductor physical design and verification
- Experience with low-technology nodes (8nm, 5nm, 3nm, or 2nm)
- Expertise in physical verification methodologies and sign-off processes
- Ability to develop and manage automated verification flows and scripts
- Bachelor's or Master's degree in engineering

## Nice to have

- Technical leadership experience mentoring junior engineers
- Knowledge of design-for-test (DfT) collaboration
- Familiarity with package and technology integration

Apply on Samsung Semiconductor's site: https://sec.wd3.myworkdayjobs.com/en-US/Samsung_Careers/job/Physical-Verification-and-EMIR-Signoff-Lead_R109845