# Physical Design Backend Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/b1b7154d-18f9-4736-ad91-eb46fe4f71a2

Listed on NVIDIA's own careers site. Applications go to them directly.

- Seniority: Entry

## Summary

NVIDIA seeks a physical design engineer to develop high-speed networking chips, working on the full RTL-to-GDS flow from synthesis through timing closure and verification. This role suits engineers with 2+ years of experience in chip design who want to tackle complex timing and power challenges on cutting-edge silicon.

_Our summary, not NVIDIA's wording._

## Skills named

Cadence OrCAD/Allegro, Static Timing Analysis

## Required

- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering
- 2+ years of physical design experience
- Experience with RTL2GDS flows
- Knowledge of PNR and STA methodologies
- Understanding of physical design and integration
- Experience with LVS/DRC verification
- Familiarity with EDA tools like Synopsys or Cadence

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Yokneam/Physical-Design-Backend-Engineer_JR2021981