# Director, Silicon Design Engineering

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/adb6c47b-dd1d-4b48-8ea1-e137d1cf8872

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Salary: 220920 – 311890 USD per year

## Summary

A Physical Design Timing Engineer role focused on analyzing and optimizing timing, power, and performance for Intel's next-generation System-on-Chip products. This position suits experienced engineers with deep expertise in static timing analysis, SoC clocking, and cross-functional collaboration who want to shape the future of semiconductor design.

_Our summary, not Intel's wording._

## Skills named

Performance Analysis, Static Timing Analysis, Tcl

## Required

- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 12+ years of timing analysis or physical design experience (or 8+ years with Master's degree, or 6+ years with PhD)
- Proficiency in static timing analysis and timing constraint generation
- Experience with physical design tools, flows, and methodologies
- Knowledge of SoC clocking and timing budgeting
- Scripting capability in TCL
- Understanding of digital design fundamentals and power/performance optimization

## Nice to have

- Signal and power integrity analysis experience
- Cross-functional collaboration demonstrated with architecture and design teams
- Problem-solving ability on complex, large-scale designs
- Experience with advanced process nodes
- Familiarity with industry-leading EDA tools

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-California-Santa-Clara/Director--Silicon-Design-Engineering_JR0284973