# Principal Collateral Device Engineer

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/9c7b935e-b335-4ab3-9aa5-819978012c18

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Principal
- Salary: 224970 – 317600 USD per year

## Summary

This role leads device engineering efforts for Intel's foundry operations, developing next-generation semiconductor process technology and collateral. It suits experienced CMOS device engineers who combine deep physics knowledge with cross-functional leadership and can bridge design, process, and yield disciplines.

_Our summary, not Intel's wording._

## Skills named

Data Analysis, Scripting, Statistical Process Control (SPC)

## Required

- Master's degree in Electrical Engineering, Physics, or related field
- 15+ years CMOS device engineering experience with focus on test chip design and device collateral development

## Nice to have

- Ph.D. in Electrical Engineering, Physics, or related field
- Advanced node test chip design experience (3nm-16nm FinFETs, sub-3nm GAA FETs)
- Design rule checker (DRC) development and physical verification flow experience
- High-Volume Manufacturing and yield monitoring experience
- Statistical process control (SPC) and advanced data analytics knowledge
- Mask generation knowledge including Boolean/OPC

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-California-Santa-Clara/Principal-Collateral-Device-Engineer_JR0285235