# Senior Physical Design Engineer (CPU)

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/9bb6b877-a3c2-41c7-937e-8262e5504ce6

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: Hillsboro, OR
- Salary: 141910 – 269100 USD per year

## Summary

This role involves owning the physical design and implementation of CPU core blocks, executing the full RTL-to-GDS flow including synthesis, place-and-route, and timing closure. It suits experienced hardware engineers with deep expertise in digital design tools and a track record of shipping complex silicon at advanced process nodes.

_Our summary, not Intel's wording._

## Skills named

Cadence OrCAD/Allegro, Perl, Python, Static Timing Analysis, Tcl

## Required

- Bachelor's degree in Computer or Electrical Engineering (or related field) with 7+ years of relevant experience, or Master's degree with 4+ years of experience
- Experience with integrated circuit design tools (Synopsys or Cadence) including logic synthesis, place and route, STA, and design closure
- PV convergence including static timing and power analysis
- Chip physical design verification (formal equivalence, timing, electrical rules, DRC/LVS, noise, electro-migration)
- Scripting in TCL plus at least one other interpreted language (Perl, Python, Ruby)
- Experience synthesizing a digital logic block integrated into a large SoC or IP

## Nice to have

- CPU micro-architecture industry experience or exposure
- Physical design best practices in floor-planning, routing, and clock distribution
- Expertise in static timing analysis, noise analysis, and reliability verification
- RTL to GDS methodologies and formal equivalence
- Synopsys Fusion Compiler, ICC2, or PrimeTime experience, or Cadence Genus/Innovus experience

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-Oregon-Hillsboro/Senior-Physical-Design-Engineer--CPU-_JR0284897
