# Senior ASIC Timing Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/9b6ded1c-82d0-44fc-bd68-26f5be293ec5

Listed on NVIDIA's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Salary: 136000 – 264500 USD per year

## Summary

NVIDIA is seeking an experienced engineer to lead timing analysis and closure for their advanced GPU and SoC designs, working across multiple levels of hierarchy from blocks to full chips. This role suits someone with deep expertise in static timing analysis, physical design optimization, and experience converging timing on cutting-edge semiconductor nodes.

_Our summary, not NVIDIA's wording._

## Skills named

Static Timing Analysis

## Required

- BS in Electrical or Computer Engineering with 5+ years of timing/STA experience, or MS with 3+ years
- Full-chip or sub-chip Static Timing Analysis and timing convergence experience
- Timing path analysis and ECO fixes including crosstalk and noise analysis
- Physical design and optimization experience to improve timing and power
- Deep knowledge of industry standard STA and timing convergence tools
- Experience with deep sub-micron process nodes

## Nice to have

- Domain-specific STA experience with GPUs, CPUs, LPUs, or SoCs
- Logic synthesis and equivalence checking or formal verification background
- DFT logic understanding and DFT timing closure experience across multiple modes
- Timing closure experience with analog/mixed-signal designs and macros
- Methodology and flow development or automation experience

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Timing-Engineer_JR2017336