# Senior DFT Power Methodology Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/94635d28-3bf7-481b-9c7f-827127d5bb0a

Listed on NVIDIA's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 196000 – 368000 USD per year

## Summary

This role involves developing design-for-test power methodology for NVIDIA's datacenter GPUs, working on low-power solutions, thermal management, and post-silicon analysis. It suits senior chip design engineers with deep DFT and power expertise who enjoy solving complex semiconductor manufacturing challenges and mentoring others.

_Our summary, not NVIDIA's wording._

## Skills named

Statistical Analysis, Very Large Scale Integration (VLSI)

## Required

- 12+ years DFT design and power experience (or MSEE with 10+ years, or PhD with 6+ years)
- Understanding of DFT fundamentals and VLSI power, timing, and voltage noise
- Statistical tools expertise for data analysis
- Multi-functional knowledge including RTL, clocks, STA, place-and-route, and power
- Silicon debug and bring-up experience on ATE or SLT platforms
- Ability to apply programming concepts to AI coding harnesses
- Strong written and oral communication skills

## Nice to have

- Power Analysis, Thermal Analysis, and IR Drop tools experience
- AI application for EDA problem-solving
- DFT Power Methodology management experience
- Post-silicon debug experience for thermal and IR Drop
- Deep technology understanding and passion

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFX-Power-Methodology-Engineer_JR2018255