# Principal Engineer - Standard Cell Design

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/814ecc3e-0d12-4154-8fb7-6f3d19597797

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Principal
- Salary: 220920 – 311890 USD per year

## Summary

Intel is seeking a Principal Engineer to lead the design and optimization of standard cell libraries that form the foundation of their semiconductor products. This role combines deep circuit design expertise with technical leadership, requiring someone who can drive innovation in power, performance, and area optimization while mentoring engineers and collaborating across product and technology teams.

_Our summary, not Intel's wording._

## Skills named

Layout Design

## Required

- Ph.D. or Master's degree in related field
- 10+ years of industry experience with foundation IP design, design-technology co-optimization, and advanced semiconductor technology
- In-depth understanding of MOSFET electrical characteristics and transistor physics at advanced nodes
- Working knowledge of transistor-level design of static circuits including latches and flip-flops
- Understanding of standard cell circuit design tradeoffs across power, performance, area, and Vmin
- Experience with standard cell characterization tools and Spice simulation
- Experience identifying, designing, and verifying cells to improve product-level PPA
- Ability to lead data analysis, identify trends, and communicate conclusions
- Expertise in low-power and high-performance circuit techniques including clocking and sequential elements
- Ability to proactively support development of junior engineers

## Nice to have

- Track record of technical leadership and delivery
- Experience designing around local layout effects and technical leadership or management
- Understanding of block-level design tools for optimizing standard cell library content
- Background in compact modeling, characterization, or EDA tool interaction
- Experience working across CPU, GPU, or SoC design teams
- Publications, patents, or recognized technical contributions
- Experience leading working groups or driving cross-organizational technical alignment

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-California-Santa-Clara/Principal-Engineer---Standard-Cell-Design_JR0285360-1