# ASIC Implementation Engineer PD

Hiring organization: [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc)

Canonical page: https://career.thegoodapps.co/jobs/81422313-516a-4329-8dc9-ecfdb3a80139

Listed on Broadcom Inc.'s own careers site. Applications go to them directly.

- Seniority: Senior
- Location: San Jose, CA
- Salary: 121900 – 195000 USD per year

## Summary

Broadcom seeks a physical design engineer to lead chip floorplanning and top-level integration for AI and PCIe switch products, from RTL through tape-out. This role suits experienced engineers with deep expertise in hierarchical floorplanning, clock trees, and cross-functional coordination across design and package teams.

_Our summary, not Broadcom Inc.'s wording._

## Skills named

Clock Tree Synthesis, Perl, Physical Design, Python, Tcl

## Required

- Floorplanning expertise in die size estimation, partitioning, clocking, and pin planning
- Experience resolving chip-level DRC/LVS/EMIR issues on advanced nodes
- On-site work required at San Jose location

## Nice to have

- Bachelor's degree in Electrical Engineering with 8+ years of top-level floorplanning experience, or Master's degree with 6+ years
- Experience with Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, and chiplet technologies
- Track record with bump planning, RDL implementation, and multi-voltage domain designs
- Hierarchical floorplanning and structured clock experience
- Collaboration experience with design, package, and methodology teams
- Scripting language proficiency

Apply on Broadcom Inc.'s site: https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-CA-San-Jose-Innovation-Drive/ASIC-Implementation-Engineer-PD_R026204