# Senior ASIC Timing Engineer, DFT

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/7f8f1d54-91dd-473c-aca4-9e1a7d633611

Listed on NVIDIA's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 136000 – 264500 USD per year

## Summary

NVIDIA is seeking an engineer to drive timing analysis and closure for design-for-test logic across their GPU and processor chips, working across multiple hierarchical levels and collaborating with multiple teams to meet timing constraints. This role suits someone with strong static timing analysis expertise and several years of experience closing timing on advanced semiconductor nodes.

_Our summary, not NVIDIA's wording._

## Skills named

Static Timing Analysis, SystemVerilog, Verilog

## Required

- BS in Electrical or Computer Engineering with 5+ years experience, or MS with 2+ years experience
- Hands-on experience with Static Timing Analysis and driving timing convergence at full-chip/sub-chip level on advanced technology nodes
- Expertise in analyzing and fixing timing paths through ECOs
- Expertise in developing timing constraints
- In-depth knowledge of industry-standard timing convergence tools

## Nice to have

- Understanding of DFT logic and experience with DFT timing closure for scan, iJTAG, and other modes
- Background in domain-specific STA such as Serdes, Processor, IO, or SMVA
- Experience in methodology or workflow development

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Timing-Engineer--DFT_JR2014685