# RTL integration Engineer

Hiring organization: [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc)

Canonical page: https://career.thegoodapps.co/jobs/749f8dce-a0f2-405b-b42c-014d2c2bf868

Listed on Broadcom Inc.'s own careers site. Applications go to them directly.

- Seniority: Senior
- Location: San Jose, CA
- Salary: 143800 – 230000 USD per year

## Summary

This role focuses on integrating and verifying IP blocks within SoCs using RTL design and simulation, requiring expertise in CDC analysis, synthesis, and gate-level debugging. It suits engineers with 12+ years of experience in design verification and implementation who can work independently on complex timing and cross-domain challenges.

_Our summary, not Broadcom Inc.'s wording._

## Skills named

SystemVerilog

## Required

- 12+ years of related experience
- Bachelor's degree
- Extensive knowledge of implementation, synthesis, and timing issues
- Strong understanding of UVM and SystemVerilog
- Deep familiarity with zero-delay and SDF simulations and debugging
- Proven gate-level simulation experience
- Familiarity with CDC analysis for RTL and gate-level designs
- Ability to work independently with minimal supervision
- Strong debugging skills

## Nice to have

- Experience with NCSim and VCS simulation tools
- Experience working in global teams
- Strong ability to learn and adapt to new tools and methodologies

Apply on Broadcom Inc.'s site: https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-CA-San-Jose-Innovation-Drive/RTL-integration-Engineer_R026729