# Lead Analog SerDes Architect/Design Engineer

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/6dd39ab7-e817-4c89-955d-d957b01eac4e

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 220920 – 311890 USD per year

## Summary

Intel seeks a lead analog circuit designer to architect high-speed SerDes components for next-generation optical interconnects in data centers, advancing their silicon photonics technology from 400G to 1.6T+ speeds. This role suits experienced mixed-signal IC designers comfortable guiding teams through complex analog CMOS blocks and collaborating across digital and physical design disciplines.

_Our summary, not Intel's wording._

## Skills named

Analog Circuit Design, Verification and Validation

## Required

- MS in Electrical Engineering
- 8+ years high-speed serial links experience
- Deep sub-micron CMOS/BiCMOS design
- Hands-on circuit design of SerDes blocks at 28Gbps+ data rates
- Precision analog circuit design (ADC/DAC)
- PAM4/NRZ link design
- Full-chip design and verification experience

## Nice to have

- Optical communications familiarity
- 400G/800G/1.6T optical link experience
- Package and test setup design experience

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-California-Santa-Clara/Lead-Analog-SerDes-Architect-Design-Engineer_JR0278355