# Sr. ASIC Layout Design Engineer

Hiring organization: [FLIR Systems](https://career.thegoodapps.co/organizations/flir-systems)

Canonical page: https://career.thegoodapps.co/jobs/6a3a6bcc-5956-485b-ae0c-41be3d3a5379

Listed on FLIR Systems's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Goleta, CA
- Salary: 113600 – 151400 USD per year

## Summary

Teledyne seeks an experienced layout engineer to design the semiconductor layouts for infrared imaging chips used in defense, medical, and scientific applications. You'll work with analog and digital design teams to translate schematics into high-performance integrated circuits, managing signal integrity and manufacturing constraints from concept through production.

_Our summary, not FLIR Systems's wording._

## Skills named

Cadence OrCAD/Allegro, Python, Siemens, Tcl

## Required

- Bachelor's degree in engineering or related field
- 10+ years of industry experience
- Expertise in analog/mixed-signal CMOS layout design
- Experience with 180nm, 130nm, or 75nm process nodes
- Proficiency in Cadence Virtuoso XL
- Understanding of Calibre verification
- Custom cell-based layout and floor planning experience
- Knowledge of wire resistance and coupling capacitance
- Excellent communication and multidisciplinary teamwork
- US Citizen or PERM Resident

## Nice to have

- Focal-plane array design experience
- Programming or scripting skills

Apply on FLIR Systems's site: https://flir.wd1.myworkdayjobs.com/en-US/flircareers/job/US---Goleta-CA/Sr-ASIC-Layout-Design-Engineer_REQ33880