# Design For Test Engineer IV (IC)

Hiring organization: [Arrow Electronics](https://career.thegoodapps.co/organizations/arrow-electronics)

Canonical page: https://career.thegoodapps.co/jobs/626d38c0-f932-4d93-bb67-997a1f8b0add

Listed on Arrow Electronics's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: San Jose, CA
- Salary: 112200 – 170500 USD per year

## Summary

This role involves implementing Design-For-Test strategies on advanced networking chips, including scan insertion, pattern generation, and memory built-in self-test verification. It's suited for an experienced test engineer comfortable with industry-standard DFT tools and semiconductor design flows.

_Our summary, not Arrow Electronics's wording._

## Skills named

Perl, Tcl

## Required

- 5–7 years of DFT experience
- Scan insertion, ATPG, and pattern simulation expertise
- MBIST insertion and verification
- IEEE 1149.1 JTAG insertion and verification
- Scripting in Perl, Shell, or TCL
- Experience with multi-million gate count SoCs in networking or consumer domains
- Mentor Tessent proficiency
- Bachelor's degree in Microelectronics or Electronics

## Nice to have

- Low power DFT experience
- Familiarity with PLL and Serdes IP blocks

Apply on Arrow Electronics's site: https://arrow.wd1.myworkdayjobs.com/en-US/AC/job/US-CA-San-Jose-California/Design-For-Test-Engineer-III--IC-_R242745