# Analog/Mixed Signal Verilog Modeling Design Engineer

Hiring organization: [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc)

Canonical page: https://career.thegoodapps.co/jobs/4b7c2710-3d5e-412b-81d6-f620fa601c4c

Listed on Broadcom Inc.'s own careers site. Applications go to them directly.

- Seniority: Senior

## Summary

This role develops behavioral models of analog circuit blocks in SystemVerilog for chip verification, bridging the analog design and digital verification teams. It suits engineers with strong analog circuit knowledge who can code detailed mixed-signal simulations and validate them against schematics.

_Our summary, not Broadcom Inc.'s wording._

## Skills named

Cadence OrCAD/Allegro, Perl, Python, SystemVerilog, Tcl

## Required

- 8+ years of related experience
- SystemVerilog DMS modeling of analog IPs
- Understanding of Verilog-AMS modeling language
- Knowledge of SystemVerilog UDT/UDR nettype
- Familiarity with analog circuits: LDOs, TIAs, analog muxing, SARADC, comparators, DACs, buffers, amplifiers
- RTL coding for digital logic and testbench creation
- SV vs. schematic verification capability
- Experience with Cadence simulation and linting tools
- Scripting in TCL, Perl, or Python

## Nice to have

- Experience using AI tools such as Cursor or chipAgents for model generation
- Familiarity with analog schematic editors

Apply on Broadcom Inc.'s site: https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-CA-Irvine-Alton-Parkway-Bldg-1/Analog-Mixed-Signal-Verilog-Modeling-Design-Engineer_R024672