# FPGA Engineer Engineer (eInfochips)

Hiring organization: [Arrow Electronics](https://career.thegoodapps.co/organizations/arrow-electronics)

Canonical page: https://career.thegoodapps.co/jobs/3d1e170c-14ec-4ce6-869b-369336293759

Listed on Arrow Electronics's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior

## Summary

This is a senior FPGA design role requiring nearly a decade of experience with digital logic, EDA tools, and high-speed protocols like PCIe and AXI. The position suits someone with deep expertise in RTL design, timing analysis, and low-power design techniques who can work on-site at a semiconductor services company.

_Our summary, not Arrow Electronics's wording._

## Skills named

Azure Resource Manager (ARM), Perl, Python, Static Timing Analysis, SystemVerilog, Tcl, Verilog

## Required

- 9+ years of experience
- 5+ years of Verilog design experience
- Proficiency in Verilog and SystemVerilog
- Knowledge of EDA tools (Fusion Compiler, CDC checkers)
- Experience with PCIe designs and protocols
- Experience with AXI, APB, and other standard interface protocols
- ARM Fabric IP experience
- Understanding of computer architecture
- Scripting ability in Python, Tcl, or Perl
- Proficiency in UPF and low-power design
- Knowledge of clock crossing techniques
- Understanding of Static Timing Analysis
- Day-1 onsite at San Jose CA or Austin TX
- Ability to travel to client locations as needed
- Ability to report progress to customers

## Nice to have

- IPXACT experience
- AMBA AXI bus and ARM or C-based processor experience

Apply on Arrow Electronics's site: https://arrow.wd1.myworkdayjobs.com/en-US/AC/job/US-CA-San-Jose-California/FPGA-Engineer-Engineer--eInfochips-_R245638