# Physical Verification Engineer

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/2e526353-402c-45a9-a569-8058a11f02cf

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Salary: 128880 – 245160 USD per year

## Summary

This role supports Intel's foundry customers with advanced semiconductor layout verification and parasitic extraction challenges, focusing on aerospace and defense applications. It suits experienced engineers who can provide technical leadership, develop verification methodologies, and guide customers through complex physical design problems on cutting-edge process nodes.

_Our summary, not Intel's wording._

## Skills named

Perl, Python, Shell Scripting, Tcl

## Required

- US citizenship
- Ability to obtain US Government Security Clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM field
- 3+ years experience with advanced CMOS processes 22nm and below
- 3+ years combined experience with layout verification and parasitic extraction EDA tools
- 3+ years experience with Python, Perl, Tcl, or shell scripting

## Nice to have

- Active US Government Security Clearance at Secret level or higher
- Post-graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM field
- Hands-on experience with LVS, DRC, ERC, or PERC
- Experience with StarRC, Quantus, or xACT parasitic extraction tools
- Experience with ICV, Calibre, or Pegasus layout editing tools
- Rule deck coding experience in ICV, Calibre, or Pegasus
- Experience providing technical direction to engineering teams
- Customer-facing technical support experience

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-Arizona-Phoenix/Physical-Verification-Engineer_JR0284076