# Lead ASIC Design Engineer

Hiring organization: [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc)

Canonical page: https://career.thegoodapps.co/jobs/239becd3-eab8-4013-a240-5fc5ff824aed

Listed on Broadcom Inc.'s own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Principal
- Location: San Jose, CA
- Salary: 143800 – 230000 USD per year

## Summary

This role leads the digital design of next-generation chips from architecture through tape-out, requiring deep expertise in RTL, synthesis, timing, and cross-team coordination. It suits experienced ASIC engineers ready to own a complete silicon project as the primary technical authority.

_Our summary, not Broadcom Inc.'s wording._

## Skills named

Cadence OrCAD/Allegro, Perl, Python, SystemVerilog, Tcl, Verilog

## Required

- 12+ years ASIC/SoC digital design experience
- Proven track record as design lead or owning chip projects
- Expert-level SystemVerilog/Verilog proficiency
- Deep experience with synthesis and STA EDA tools
- History of successful first-pass silicon tape-outs on modern process nodes
- Outstanding documentation and communication skills
- Legal US work authorization
- Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field

## Nice to have

- Mixed-signal or high-speed PHY architecture experience (SerDes, PCIe, DDR, custom interconnects)
- DFT planning and scan insertion experience
- Scripting proficiency (Python, Tcl, Perl)

Apply on Broadcom Inc.'s site: https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-California-San-Jose-1320-Ridder-Park-Drive/Lead-ASIC-Design-Engineer_R026296