# Design Verification Engineer

Hiring organization: [Baidu](https://career.thegoodapps.co/organizations/baidu)

Canonical page: https://career.thegoodapps.co/jobs/20021c43-69dd-4d26-845c-a11a225f25c1

Listed on Baidu's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Sunnyvale, CA

## Summary

This role verifies the functionality of AI accelerator chips at Baidu's Sunnyvale office, requiring someone with deep UVM and SystemVerilog expertise to develop testbenches, run simulations, and close coverage across block and system levels. It suits experienced verification engineers who want to work on cutting-edge AI silicon and thrive in a fast-paced technical environment.

_Our summary, not Baidu's wording._

## Skills named

Perl, Python, SystemVerilog, Tcl

## Required

- Minimum 5 years of UVM-based verification experience on complex projects
- Advanced knowledge of ASIC design and verification flows
- Advanced SystemVerilog and UVM methodology expertise
- Proficiency in constrained random testing, coverage closure, and gate-level simulation
- Experience with at least one high-speed interface (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)
- Fluency in English and Chinese

## Nice to have

- Scripting language experience (Perl, Python, Tcl)
- C/C++ familiarity
- Formal verification experience (Model Checking, Equivalence Checking)
- Mixed-signal co-simulation and emulation experience

Apply on Baidu's site: https://job-boards.greenhouse.io/baidu/jobs/3234390