# Senior FPGA Engineer

Hiring organization: [Astranis](https://career.thegoodapps.co/organizations/astranis)

Canonical page: https://career.thegoodapps.co/jobs/1f269e76-42a1-4bd7-9298-74a49338e20f

Listed on Astranis's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: San Francisco, CA
- Salary: 175000 – 240000 USD per year

## Summary

Astranis is seeking a Senior FPGA Engineer to design and verify RTL for spacecraft and ground station FPGAs used in satellite communications systems. This role suits engineers with 5+ years of FPGA experience who can work across high-performance radio, avionics, and ground systems for commercial and government projects.

_Our summary, not Astranis's wording._

## Skills named

C++, FPGA, SystemVerilog, Tcl, Verilog, Vivado

## Required

- Bachelor of Science in electrical engineering, computer science, computer engineering, or equivalent
- 5+ years of FPGA design experience
- Experience designing, implementing, and testing high throughput FPGA systems
- Strong proficiency in Verilog/SystemVerilog for synthesis and verification
- Experience writing test benches and FPGA verification at module and system level
- Experience with C/C++ bit-accurate RTL modeling
- Familiarity with power, thermal, and area implications of designs
- U.S. citizenship, lawful permanent residency, or protected refugee/asylee status

## Nice to have

- Master's or PhD in computer engineering or equivalent
- Expertise in DSP/radio design, software, encryption, or FEC encoding/decoding
- Experience with Xilinx Ultrascale+/Versal FPGAs
- Experience with high-speed data converters (ADCs, DACs)
- Experience with UVM and DPI simulation methodologies
- Experience with circuit-level debugging
- Knowledge of digital communication theory, DVB-S2X, LDPC, Turbo, Reed-Solomon coding
- Experience with space-based systems and radiation-tolerant design (TMR, ECC)

Apply on Astranis's site: https://job-boards.greenhouse.io/astranis/jobs/4017405006