# Senior Physical Design Methodology Engineer, PPA Fusion Compiler

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/1e7c3299-e090-41ec-8f9d-5a9e6759e6ea

Listed on NVIDIA's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Salary: 168000 – 310500 USD per year

## Summary

NVIDIA is seeking a Senior Physical Design Methodology Engineer to develop advanced physical design methodologies and machine learning-based solutions for their high-performance GPU and system-on-chip designs. This role suits experienced chip design professionals with expertise in place-and-route, timing closure, and power/performance optimization who want to work on cutting-edge computing hardware.

_Our summary, not NVIDIA's wording._

## Skills named

Machine Learning, Scripting

## Required

- Master's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience)
- 10+ years of physical design engineering experience
- Proven implementation of ML-based solutions in chip design
- Experience with floorplanning, clock and power distribution, place and route, integration and verification
- Knowledge of timing and electromagnetic convergence with power integrity
- Hierarchical design approach and top-down design methodology
- Experience with design for yield, manufacturability, EM and IR closure, and thermal management
- Proficiency with industry standard place-and-route and analysis tools
- Capability to write extensive scripts for PPA analysis and improvement

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Physical-Design-Methodology-Engineer--PPA-Fusion-Compiler_JR2011273