# Senior DFT Power Methodology Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/1cd3ff68-4930-462f-8c7c-d950bf466cb8

Listed on NVIDIA's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 168000 – 310500 USD per year

## Summary

This role involves developing design-for-test power methodologies and enabling advanced AI techniques to optimize thermal management and quality for NVIDIA's next-generation datacenter GPUs. You'll partner across teams to solve complex semiconductor manufacturing challenges while mentoring junior engineers on test design trade-offs.

_Our summary, not NVIDIA's wording._

## Skills named

Machine Learning, Static Timing Analysis, Statistical Analysis, Very Large Scale Integration (VLSI)

## Required

- BSEE with 12+ years experience in DFT and power, or MSEE with 10+ years, or PhD with 6+ years
- Fundamental DFT and VLSI knowledge in power, timing, and voltage noise
- Power, thermal, and voltage noise analysis experience
- Statistical tools expertise for data analysis
- Exposure to RTL, clocks, STA, place-and-route, and power design areas
- Silicon debug and bring-up experience on ATE or SLT platforms
- Ability to think programmatically for AI-based solutions

## Nice to have

- Power Analysis, Thermal Analysis, and IR Drop tools experience
- AI application for EDA problem-solving
- DFT Power Methodology management experience
- Post-silicon debug experience for thermal and IR Drop
- Technology understanding and passion for the domain

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Power-Methodology-Engineer_JR2021098-1