# Physical Design Engineer

Hiring organization: [Ambarella](https://career.thegoodapps.co/organizations/ambarella)

Canonical page: https://career.thegoodapps.co/jobs/16f617da-9b6f-444e-82ff-b56b6d66aac9

Listed on Ambarella's own careers site. Applications go to them directly.

- Seniority: Mid
- Location: US Headquarters
- Salary: 140000 – 156000 USD per year

## Summary

This role involves designing and optimizing the physical layout of advanced AI processor chips, from initial floorplanning through final verification and tape-out. It suits engineers with several years of experience in digital chip design who want to work on cutting-edge low-power SoCs using industry-standard tools.

_Our summary, not Ambarella's wording._

## Skills named

Make (Integromat), Perl, Python, Tcl, Verilog, VHDL

## Required

- BS/MS in EE or computer science, or equivalent experience
- 3–5+ years of VLSI digital design and layout experience
- Good understanding of VLSI digital design, layout, and timing closure
- Basic knowledge of circuit design, device delays, and timing at gate level
- Proficiency with Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/Primetime, or Mentor Calibre
- Programming and scripting in Perl, Python, TCL, C-shell, or make
- Knowledge of Verilog or VHDL
- Self-motivated with strong communication skills

## Nice to have

- Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC
- Deep understanding of hierarchical physical design strategies and nanometer technology issues
- Hands-on STA experience with multi-mode multi-corner analysis
- Track record of delivering tape-out quality GDSII with silicon success in sub-10 nm nodes

Apply on Ambarella's site: https://ambarella.wd108.myworkdayjobs.com/en-US/Ambarella/job/US-Headquarters/Physical-Design-Engineer_JR100284