# STA Lead Engineer

Hiring organization: [Samsung Semiconductor](https://career.thegoodapps.co/organizations/samsung-semiconductor)

Canonical page: https://career.thegoodapps.co/jobs/0a36148c-937b-4b9a-b6ae-9a82b8e2b061

Listed on Samsung Semiconductor's own careers site. Applications go to them directly.

- Seniority: Senior

## Summary

Lead a team of STA engineers in semiconductor design, taking ownership of timing closure, synthesis, and physical design optimization for advanced chips. This role suits experienced ASIC design professionals who excel at both technical execution and mentoring, with deep expertise in constraints, low-power design, and high-speed timing closure.

_Our summary, not Samsung Semiconductor's wording._

## Skills named

Perl, Static Timing Analysis, Tcl, Verilog

## Required

- BSEE or MSEE in electrical engineering
- 12+ years of ASIC design experience
- Hands-on technical expertise in synthesis and STA
- Strong written and oral communication
- Deep sub-micron design knowledge
- Experience leading hard-IP and SoC timing closure
- Functional and test mode constraint development
- Low power management understanding
- Perl or Tcl scripting
- Ability to mentor and lead teams

## Nice to have

- Good understanding of APR flows
- Experience with constraint management tools
- Knowledge of cross-talk noise analysis
- GCA and VCLP experience

Apply on Samsung Semiconductor's site: https://sec.wd3.myworkdayjobs.com/en-US/Samsung_Careers/job/STA-Lead-Engineer_R109848