# Design Verification Engineer

Hiring organization: [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc)

Canonical page: https://career.thegoodapps.co/jobs/09f7ce5e-fa38-4a4a-8354-e1160d56eb9c

Listed on Broadcom Inc.'s own careers site. Applications go to them directly.

- Seniority: Senior
- Salary: 143800 – 230000 USD per year

## Summary

Broadcom's ASIC division seeks a verification engineer to design and validate complex digital and mixed-signal IP blocks, from initial planning through coverage closure and debug. This role suits someone with deep SystemVerilog and UVM expertise who can architect reusable verification environments and work across block, system, and ASIC levels.

_Our summary, not Broadcom Inc.'s wording._

## Skills named

Cadence OrCAD/Allegro, Git, Perl, Python, SystemVerilog, Tcl

## Required

- 12+ years verification experience for complex digital and mixed-signal circuits
- Block and system level design verification
- Complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
- RTL and gate-level netlist debugging
- SystemVerilog and UVM
- Advanced verification methodologies including SVA
- Synopsys, Cadence, Mentor simulation tools
- Perl, Python, or Tcl scripting
- Version control systems experience
- Reusable and scalable verification environment design
- BS in Electrical/Computer Engineering with 12+ years experience OR MS in Electrical/Computer Engineering with 10+ years experience
- Legal authorization to work in the US

## Nice to have

- Hardware design and debug experience
- Emulation platform experience (Palladium, Veloce, Zebu)
- FPGA platform experience (Xilinx)
- Formal verification experience
- iJTAG network verification using ICL and PDL in Tessent tool
- Co-simulation experience

Apply on Broadcom Inc.'s site: https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-CO-Broomfield/Design-Verification-Engineer_R026745