# Senior ASIC Physical Design Engineer, Netlisting

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/05aaf3d3-3112-4d30-ab24-4bf5fbf5cf3c

Listed on NVIDIA's own careers site. Applications go to them directly.

- Seniority: Senior
- Salary: 136000 – 264500 USD per year

## Summary

This Senior ASIC Physical Design Engineer role focuses on netlist-related work during chip design, handling logic equivalence checking, timing analysis, and synthesis for GPUs and SoCs at NVIDIA. It suits experienced hardware engineers with deep expertise in formal verification, EDA tools, and timing closure who want to work on cutting-edge AI computing hardware.

_Our summary, not NVIDIA's wording._

## Skills named

Make (Integromat), Perl, Python, Static Timing Analysis, Tcl

## Required

- BS in Electrical or Computer Engineering with 5+ years experience, or MS with 3+ years experience
- Expertise in logic equivalence checking and formal verification from RTL to tapeout
- Experience with clock-domain-crossing checking and MTBF analysis
- Logic synthesis experience at block or full-chip level
- Full-chip or sub-chip Static Timing Analysis expertise and timing constraint management
- Knowledge of industry-standard EDA tools
- Proficiency in Perl, TCL, Make, or Python

## Nice to have

- Experience in logic synthesis and equivalence checking with industry tools
- Strong debugging and problem-solving skills
- Background in DFT timing closure for scan, transition faults, and BIST modes
- Experience or drive to improve workflows through AI utilization

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Physical-Design-Engineer--Netlisting_JR2021166